Embodiments of the present disclosure relate generally to semiconductor devices and, more particularly, to semiconductor devices including pipe latch units.
In general, double data rate 2 (hereinafter referred to as “DDR2”) synchronous dynamic random access memory (hereinafter referred to as “SDRAM”) devices may successively receive a plurality of commands from external devices. Even in this case, however, operations corresponding to the commands are not immediately executed in the DDR2 SDRAM device. When the DDR2 SDRAM devices are under a write operation mode, column address strobe (hereinafter referred to as “CAS”) signals should be activated. Therefore, the DDR2 SDRAM devices that successively received a plurality of commands including a read command may secure an execution time for various other operations by delaying a point when the CAS is activated. A delay time from input of a read command till an activation of the CAS is referred to as an additive latency (hereinafter referred to as “AL”). Further, a CAS latency (hereinafter referred to as “CL”) denotes a delay time from the activation of the CAS till output of valid data. That is, a read latency (hereinafter referred to as “RL”) from the input of the read command till the output of the valid data may correspond to a sum of the AL and the CL. The AL and the CAS may be represented by the number of clock cycles.
The DDR2 SDRAM device may store the data, outputted from cell array blocks by the read command, in a latch circuit and may output the data stored in the latch circuit through the output pins at a point when the CL terminates. This is for preventing the data from colliding with each other when at least one of the data is outputted from cell array blocks earlier than a predetermined CL.
A plurality of data bits may be outputted by applying the read command once, and the number of data bits outputted consecutively may be determined by a burst length (hereinafter referred to as “BL”) of a mode register set (hereinafter referred to as “MRS”). Further, an output sequence of the data may also be determined by a burst type of the MRS. Therefore, a data output mode of the DDR2 SDRAM devices may be categorized as either an interleave mode or a sequential mode according to the burst type of the MRS, and the output sequence of the data may vary according to the data output mode.
The DDR2 SDRAM devices may use a four-bit pre-fetch scheme that transmits four bits per one data pin through a global data I/O line (hereinafter referred to as “GIO”) in a read operation mode. The pre-fetch scheme is used to overcome limitations in improving an operation speed of core region of the semiconductor devices, for example, the DDR2 SDRAM devices. The pre-fetch scheme allows data to be processed in parallel in the core region of the semiconductor devices and outputted in series through an interface between the semiconductor devices and external devices. The pre-fetch scheme may be realized by a pre-fetch circuit including a plurality of pipe latch units.